1. Field of the Invention
The present invention relates to a fabrication method of a liquid crystal display panel, and more particularly to the fabrication method of the liquid crystal display panel capable of simplifying a substrate structure and a fabrication process.
2. Description of the Related Art
In general, a liquid crystal display represents an image by means of adjusting a transmittance of the liquid crystal by use of an electric field. For this purpose, the liquid crystal display comprises a liquid crystal display panel where the liquid crystal cells are arranged in a matrix pattern, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel comprises the thin film transistor array substrate and a color filter array substrate facing each other, a spacer located for maintaining a fixed cell gap between two substrates and a liquid crystal stuffed to the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching device at every intersection of the gate lines and the data lines, a pixel electrode connected to the thin film transistor formed by the liquid crystal cell unit, and an alignment film applied on them and so on. The gate lines and the data lines are supplied with signal from driving circuits through each of the pad part. The thin film transistor responds to a scan signal supplied to the gate line, and supplies to pixel electrode a pixel voltage signal supplied to the data line.
The color filter array substrate includes a color filter formed by the liquid crystal cell unit, a black matrix for reflecting external light and separating between the color filters, a common electrode supplying a reference voltage commonly to the liquid crystal cells, and an alignment film applied on them.
The liquid crystal display panel combines the thin film transistor array substrate and the color filter array substrate. Liquid crystal is injected beteween substrates and the panel and is then sealed. This liquid crystal panel includes, a thin film transistor array substrate, whose manufacture requires a semiconductor process and a plurality of masking processes.
Accordingly, the manufacturing process is complicated, increasing the cost of the liquid crystal display panel. In order to solve this problem, the manufacture of the thin film transistor array substrate is improved so as to reduce the number of masking process number. The benefit is that in one masking process, there are many sub-processes such as an evaporation process, a cleaning process, a photolithography process, an etching process, a photoresist strip process and an inspection process. Recently, instead of the 5-step masking process which is the common masking process for thin film transistor array substrates, a 4-step masking process reducing one of the masking sub-processes has been developed.
FIG. 1 is a plane view illustrating the thin film transistor array substrate formed using a masking process, and FIG. 2 is a sectional view taken along line I-I′ of FIG. 1 illustrating the thin film transistor array substrate as shown in FIG. 1.
The thin film transistor array substrate, as shown in FIG. 1 and FIG. 2, comprises gate lines 2 and data lines 4 crossed with each other and having a gate insulation film therebetween on a lower substrate 42, a thin film transistor 6 formed at every intersection, and a pixel electrode 18 formed in the cell region arranged in the crossed pattern. And the thin film transistor array substrate comprises a storage capacitor 20 formed at overlapped part of the pixel electrode 18 and a prior stage gate line 2, a gate pad part 26 connected to the gate line 2 and a data pad part 34 connected to the data line 4.
The thin film transistor 6 comprises a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18, an active layer 14 defining a channel between the source electrode 10 and the drain electrode 12 and overlapped with the gate electrode 8. The active layer 14 overlaps with the data pad 36, the storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12, and further comprises a channel part defined between the source electrode 10 and the drain electrode 12. On the active layer 14, the data pad 36, the storage electrode 22, the data line 4, the source electrode 10, the drain electrode 12 and an ohmic contact layer 48 for making an ohmic contact are further formed. The thin film transistor 6 responds to the gate signal supplied to the gate line 2 and supplies a pixel voltage signal from the data line 4 to the pixel electrode 18.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a first contact hole 16 penetrating a protection film 50. The pixel electrode 18 generates a voltage difference from the common electrode formed on the upper substrate (not shown). By this voltage difference, the liquid crystal located between the thin film transistor substrate and the upper substrate rotates due to a dielectric anisotropy, and transmits incident light through the pixel electrode 18 from the light source (not shown) transmit to the upper substrate.
The storage capacitor 20 comprises a prior stage gate line 2, a storage electrode overlapped with the gate line 2 having the gate insulation film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and the pixel electrode 18 connected through the second contact hole 24 formed at the protection film 50 and overlapped with the storage electrode 22 having the protection film 50 therebetween. The storage capacitor 20 maintains the pixel voltage charged to the pixel electrode 18 constant until the next pixel voltage is charged.
The gate line 2 is connected to the gate driver (not shown) through the gate pad part 26. The gate pad part 26 comprises the gate pad 28 extending from the gate line 2 and the gate pad protection electrode 32 connected to the gate pad 28 through the third contact hole 30 penetrating both of the gate insulation film 44 and the protection film 50.
The data line 4 is connected to the data driver (not shown) through the data pad part 34. The data pad part 34 comprises the data pad 36 extending from the data line 4 and the data pad protection electrode 40 connected to the data pad 36 through the fourth contact hole 38 penetrating the protection film 50.
The fabrication method of the thin film transistor substrate having this constitution is explained in full detail in FIGS. 3a to 3d using a 4-step masking process.
Referring to FIG. 3a, the gate patterns are formed on the lower substrate 42.
On the lower substrate 42, the gate metal layer is formed by an evaporation method such as sputtering. Subsequently, the gate metal layer is patterned by the photolithography process using the first mask and the etching process. In addition, the gate patterns, including the gate line 2, the gate electrode 8, and the gate pad 28 are formed. As a gate metal, a chrome (Cr), molybdenum (Mo), aluminum (Al), and so on are used in a single layer or a double layer structure.
Referring to FIG. 3b, on the lower substrate 42 where the gate pattern is formed, the gate insulation film 44, the active layer 14, the ohmic contact layer 48 and source/drain patterns are subsequently formed.
On the lower substrate 42 having the gate pattern, the gate insulation film 44, an amorphous silicon layer, a n+ amorphous silicon layer and the source/drain metal layer are subsequently formed by the evaporation method such as a PECVD, a sputtering and so on.
The photoresist pattern is formed on the source/drain metal layer by a photolithography process by the use of the second mask. In this case, by using a diffraction photo mask as a second mask having the diffraction photo part over the channel part of the thin film transistor, the photoresist pattern of the channel part has lower height than the other source/drain pattern part.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photoresist pattern and therefore the source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 combined as one body with the source electrode 10 and the storage electrode 22 are formed.
In addition, by a dry etching process using the same photoresist pattern, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time and therefore the ohmic contact layer 48 and the active layer 14 are formed.
The photoresist pattern with a relatively low height is removed from the channel part by an ashing process, and then the source/drain pattern of the channel part and the ohmic contact layer 48 are etched by the dry etching process. Hereby, the active layer 14 in the channel part is exposed and the source electrode 10 and the drain electrode 12 are separated.
Subsequently, the photoresist pattern existing on the source/drain pattern part is removed by a strip process.
For the material of the gate insulation film 44, an inorganic insulation material such as a silicon oxide (SiOx) or a silicon nitride (SiNx) is used. As a source/drain metal, molybdenum (Mo), titanium (Ti), tantalum (Ta), a molybdenum alloy, and so on can be used.
Referring to FIG. 3c, on the gate insulation film 44 where the source/drain patterns are formed, the protection film 50 including the first to the fourth contact holes (16, 24, 30, 38) is formed.
On the gate insulation film 44 where the source/drain patterns are formed, the protection film 50 is wholly formed by an evaporation method such as PECVD. The protection film 50 is patterned by a photolithography process and then etched using a third mask, thereby forming the first to the fourth contact holes (16, 24, 30, 38). The first contact hole 16 penetrates the protection film 50 and is formed so as to expose the drain electrode 12. The second contact hole 24 penetrates the protection film 50 and is formed so as to expose the storage electrode 22. The third contact hole 30 penetrates the protection film 50 and the gate insulation film 44 and is formed so as to expose the gate pad 28. The fourth contact hole 38 penetrates the protection layer 50 and is formed so as to expose the data pad 6.
For the protection film 50, an inorganic insulation material such as the gate insulation film 94 or an organic insulation material such as an acryl organic compound, BCB or PFCB having a low dielectric coefficient is used.
Referring to FIG. 3d, the transparent electrode patterns are formed on the protection film 50.
The transparent electrode material is wholly evaporated on the protection film 50 by the evaporation method such as the sputtering. Subsequently, by the photolithography process and the etching process using the fourth mask, the transparent electrode material is patterned, forming the transparent electrode pattern including the pixel electrode 18, the gate pad protection electrode 32, and the data pad protection electrode 40. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16 and is electrically connected to the storage electrode overlapped with a prior stage gate line 2 through the second contact hole 24. The gate pad protection electrode 32 is electrically connected to the gate pad 28 through the third contact hole 30. The data pad protection electrode 40 is electrically connected to the data pad 36 through the fourth contact hole 38.
A transparent electrode material, such as an Indium Tin Oxide (ITO), Tin Oxide (TO), or Indium Zinc Oxide (IZO) is used. The thin film transistor substrate and the manufacturing method described above can decrease the number of steps in the manufacture process by adopting a 4-mask process rather than a 5-mask process. In addition, it can decrease the manufacturing cost proportionately. But since the manufacture process of the 4-mask process is complicated and possible cost reduction is limited, the thin film transistor substrate and a manufacturing method thereof is required that is further reduces the manufacture cost by further of simplifying the manufacture process.
Moreover, the pad part open process of the related art thin film transistor array substrate is carried out by the photolithography process. Accordingly, there is a problem in that the fabrication process is complicated and the material cost is high.